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| For Audio Equipment MN662747RPH Signal Processing LSI for CD Players Overview The MN662747RPH is a CD signal processing LSI that, on a single chip, combines optics servos for the CD player (focus, tracking, and traverse servos), digital signal processing (EFM demodulation and error correction), digital servo processing for the spindle motor, digital filter, and D/A converter, so thus covers all signal processing functions from the head's RF amplifier onward. (Audio circuits) Digital filter using 8-fold oversampling Built-in D/A converter (1-bit D/A converter) Built-in differential operational amplifier (secondary low pass filter) (Other) Built-in playback pitch control function (normal speed only) (13%) Support for quadruple-speed playback (digital servo and signal processing block only) Built-in support for jitter-free disc rotation synchronization playback Oscillator shutdown mode Power management mode Operating voltage 4.5 to 5.5 V Features (Optics servo) Focus, tracking, and traverse servos Automatic adjustment functions for FO/TR gain, FO/TR offset, and FO/TR balance Built-in D/A converter for drive voltage output Built-in dropout countermeasures Anti-shock functions Built-in track cross counter Traverse speed detection function (Digital Signal Processing) Built-in DSL and PLL Frame synchronization detection, holding, and insertion Subcode data processing Subcode Q data CRC check Built-in subcode Q data register CIRC error detection and correction C1 decoder: duplex error correction C2 decoder: triplex error correction Built-in 16-K bits of RAM for use in deinterleaving Audio data interpolation Averaging or retention of previous values Digital attenuation (-12 dB) Audio data peak level detection function Digital audio interface (EIAJ format) Audio data serial interface for input and output (Spindle Motor Servo) CLV digital servo Switchable servo gain Applications CD players MN662747RPH Pin Assignment For Audio Equipment 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 BYTCK/TVSTOP CLDCK FCLK IPFLAG FLAG CLVS CRC DEMPH FLAG6/RESY IOSEL TEST AVDD1 OUTL AVSS1 OUTR RSEL CSEL PSEL MSEL SSEL 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD X2 X1 VSS SBCK SUBC VCOF2 PCK EFM AVSS2 AVDD2 VCOF PLLF DSLF DRF IREF ARF WVEL PLAY PLLF2 LDON BDO RFDET TRCRS OFT VDET RFENV TE FE TBAL FBAL VREF FOD TRD KICK ECS ECM PC TVD TRV BCLK LRCK SRDATA DVDD1 DVSS1 TX MCLK MDATA MLD SENSE FLOCK TLOCK BLKCK SQCK SUBQ DMUTE STAT RST SMCK PMCK (TOP VIEW) QFS080-P-1414 For Audio Equipment Block Diagram 51 AVSS2 50 AVDD2 LRCKIN/MSEL BCLKIN/SSEL SRDATEIN/PSEL 70 66 67 13 62 56 55 68 69 CIRC ERROR CORRECTION 16K SRAM DEINTERLEAVE SUBCODE BUFFER MN662747RPH 8 TIMES OVER SAMPLING DIGITAL FILTER 75 PWM (R) - + DIGITAL DEEMPHASIS OUTR 1 BIT DAC LOGICS 73 PWM (L) - + OUTL IOSEL CLVS CRC BLKCK CLDCK SBCK SUBC DEMPH FLAG6/RESY 74 AVSS1 72 AVDD1 65 FLAG 64 IPFLAG DIGITAL AUDIO INTERFACE 6 TX CLV SERVO EFM DEMODULATION SYNC INTERPOLATION SUBCODE DEMODULATION 80 SSEL 14 SQCK 15 SUBQ PCK EFM PLLF PLLF2 DSLF IREF DRF ARF RSEL PSEL 53 52 48 41 47 45 46 44 76 78 24 23 ECM PC INTERPOLATION SOFT MUTING DIGITAL ATTENUATION PEAK DETECT AUTO CUE VCO 2 3 1 16 LRCK SRDATA BCLK DMUTE DSL*PLL 9 MLD 7 MCLK 8 MDATA SERVO CPU CK384/EFM 54 VCOF2 49 VCOF SMCK FCLK PMCK CSEL MSEL X2 X1 STAT 19 63 20 77 79 59 58 17 A/D CONVERTER 60 57 4 5 18 71 32 FE 33 TE 34 RFENV INPUT PORT 37 35 39 SERVO TIMING GENERATOR 38 36 D/A CONVERTER VCO TIMING GENERATOR PITCH CONTROL MICROCOMPUTER INTERFACE 21 26 29 61 25 22 27 28 31 30 12 11 42 40 TRV KICK VREF BYTCK/TRVSTOP ECS TVD TRD FOD TBAL FBAL TLOCK FLOCK PLAY LDON OUTPUT PORT 43 WVEL 10 SENSE RFDET VDD VSS DVDD1 DVSS1 RST TEST VDET TRCRS BDO OFT MN662747RPH Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 Symbol BCLK LRCK SRDATA DV DD1 DVSS1 TX MCLK MDATA MLD SENSE FLOCK or DIRBK I/O O O O I I O I I I O O For Audio Equipment Function Description SRDATA bit clock output. Left/right channel discrimination signal output. Serial data output. Power supply for digital circuits. Ground for digital circuits. Digital audio interface output signal. Microcomputer command clock input. (Data is latched at rising edge.) Microcomputer command data input. Microcomputer command load signal input. "L" level: load. Sense signal output. (OFT, FESL, NACEND, NAJEND, SFG, and NWTEND) During default operation, focus servo convergence signal. "L" level: convergence. During command execution, direction detection output for external track counter. 12 TLOCK or OTCFR O During default operation, tracking servo convergence signal. "L" level: convergence. During command execution, traverse speed control output. 13 14 15 16 17 BLKCK SQCK SUBQ DMUTE STAT O I O I O Subcode block clock signal (f BLKCK=75 Hz) External clock input for subcode Q register Subcode Q data output Muting input. (Effective only for an output bit rate of 64 fs) "H" level: muting. Status signal. (CRC, CLVS, TTSTOP, JCLVS, SQOK, FLAG6, SENSE, FLOCK, TLOCK, rpm data, and FCLV) 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RST SMCK PMCK TRV TVD PC ECM ECS KICK TRD FOD VREF FBAL TBAL FE I O O O O O O O O O O I O O I Reset input. "L" level: reset. If MSEL is "H" level, 8.4672 MHz clock signal output. If MSEL is "L" level, 4.2336 MHz clock signal output 88.2 kHz clock signal output. Traverse forced feed output. Traverse drive output. Spindle motor ON signal. "L" level: ON (default). (tristate) (tristate) (tristate) Spindle motor drive signal (forced mode output). Spindle motor drive signal (servo error signal output). Kick pulse output. Tracking drive output. Focus drive output. Reference voltage for DA output (TVD, ECS, TRD, FOD, FBAL, and TBAL). Focus balance adjustment output. Tracking balance adjustment output. Focus error signal input. (analog input) (tristate) For Audio Equipment Pin Descriptions (continued) Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Symbol TE RFENV VDET OFT TRCRS RFDET BDO LDON PLLF2 PLAY WVEL ARF IREF DRF DSLF PLLF VCOF AV DD2 AV SS2 EFM or CK384 I/O I I I I I I I O I/O O O I I I I/O I/O I/O I I O MN662747RPH Function Description Tracking error signal input. (analog input) RF envelope signal input. Vibration detection signal input. Offtrack signal input. Track cross signal input. RF detection signal input. Dropout signal input. Laser ON signal output. PLL loop filter characteristic selection pin. Play signal output. Double-speed status signal output. RF signal input. Reference current input pin. DSL bias pin. DSL loop filter pin. PLL loop filter pin. VCO loop filter pin. Power supply for analog circuits (DSL, PLL, D/A converter output, and A/D converter). Ground for analog circuits (DSL, PLL, D/A converter output, and A/D converter). EFM signal output. EFM output when IOSEL is "H" level. *Crystal oscillator 16.9344-MHz clock output when I *OSEL is "L" level. *384 f s output from signal processing block. (During variable-pitch operation, this is the VCO clock.) Commands permit switching among the above three outputs. (analog input) "H" level: vibration detected. "H" level: offtrack. (analog input) "L" level: detected. "H" level: dropout. "H" level: ON. "H" level: play. "H" level: double-speed. 53 54 55 56 57 58 59 60 61 62 63 64 65 PCK VCOF2 SUBC SBCK VSS X1 X2 VDD BYTCK or TRVSTOP CLDCK FCLK IPFLAG FLAG O or DSLB I/O O I I I O I O O O O O PLL derived clock or DSL balance output. fPCK =4.3218 MHz. VCO loop filter pin. Subcode serial output. Serial clock input for subcode serial output. Ground for oscillator circuit. Crystal oscillator circuit input/output pins. f=16.9344 MHz, 33.8688 MHz. Crystal oscillator circuit output/output pins. f=16.9344 MHz, 33.8688 MHz. Oscillator circuit power supply. When IOSEL is "H" level, byte clock signal output. When IOSEL is "L" level, traverse stop signal output. "H" level: stop mode. Subcode frame clock signal output pin. (f CLDCK=7.35 kHz) Crystal frame clock signal output. (fFCLK=7.35 kHz) Interpolation flag signal output. "H" level: interpolation. Flag signal output. MN662747RPH Pin Descriptions (continued) Pin No. 66 67 Symbol CLVS CRC or TCK 68 69 DEMPH FLAG6 or RESY O O I/O O O For Audio Equipment Function Description Spindle servo phase synchronization signal output. "H" level: CLV. "L" level: rough servo. During default operation, subcode CRC check result output. "H" level: OK. "L" level: no good. During command execution, pulse output for external track counter. De-emphasis detection signal output. "H" level: ON. When IOSEL is "L" level, FLAG6 output, signal for resetting address of RAM for error correction de-interleave. "L" level: address reset. When IOSEL is "H" level, RESY output, frame resynchronization signal. "H" level: synchronized. "L" level: out of sync. 70 71 72 73 74 75 76 77 78 79 IOSEL TEST AV DD1 OUTL AVSS1 OUTR RSEL CSEL PSEL MSEL I I I O I O I I I I Mode selection pin Test pin. audio outputs.) Left channel audio output. Ground for analog circuits. (common use for left and right channel audio outputs.) Right channel audio output. RF signal polarity selection pin. "H" level: bright level is "H." "L" level: bright level is "L." Crystal oscillator frequency specification pin. When IOSEL is "H" level, test pin. When IOSEL is "L" level, SRDATA input. When IOSEL is "H" level, frequency selection pin for SMCK pin output. "H" level: SMCK=8.4672 MHz When IOSEL is "L" level, LRCK input. "H" level: left channel data. "L" level: right channel data. SMCK output fixed at 4.2336 MHz. "H" level: 33.8688 MHz. "L" level: 16.9344 MHz Keep this at "L" level. Keep this at "H" level. Power supply for analog circuits. (common use for left and right channel 80 SSEL I When IOSEL is "H" level, SUBQ pin output mode selection pin. "H" level: buffered subcode Q mode. "L" level: CLDCK synchronization mode. When IOSEL is "L" level, BCKL input. Buffered subcode Q mode. For Audio Equipment Package Dimensions (Unit: mm) QFS080-P-1414 MN662747RPH 16.20.2 14.00.2 60 61 41 40 0.825 14.00.2 80 21 1 0.65 20 2.00.2 0.3 -0.05 2.10.3 +0.10 16.20.2 1.10.1 0 to 10 0.550.1 +0.10 -0.05 0.15 SEATING PLANE 0.10.1 0.15 |
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